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Introduction

Most of the modular PXIe products adopt an FPGA based architecture, implementing the digital interfaces to the underlined hardware such as ADC/DAC, clock and memory management, trigger and sync, etc. The off-the-shelf feature-rich functionalities of the modules and the control (e.g. IQ modulator, function generators or queue system for the AWGs or advanced triggers and DAQs for the digitizers) are also implemented in the logic.

However, standard products typically do not have available resources for additional processing functions. Some applications require the use of custom on-board real-time processing which might not be covered by the comprehensive off-the-shelf functionalities of the standard hardware products. For these applications, Keysight supplies hardware products that provide the capability to program the on-board FPGA.

M3602A FPGA programming software is compatible with M3xxxA PXIe modular hardware products. M3602A provides the necessary tools to design, compile and program the FPGA of the module. M3xxxA offering is made of AWGs and digitizers that allow engineers to build onto the instrument's core capabilities or insert custom algorithms into the on-board FPGAs. This graphical design environment makes it easy to add customization required for emerging technologies, research and design while accessing the full performance and speed of the FPGA.

M3602A a Graphical FPGA Design Environment

The M3602A FPGA Design Environment provides a graphical FPGA programmable environment that allows for customization capability. To take advantage of the M3602A software, it is important to order the -FP1 hardware option when purchasing the hardware. When configuring the hardware with option -FP1, select which FPGA wanted to be loaded on the hardware. FPGAs that needs to work with option -FP1 are bigger than those that come with the standard hardware.

The M3602A software enables non-expert and expert users to achieve high-performant solutions (e.g. loop control for DRFM, DPD* filtering for AWGs, data compression*, frequency masking, for data acquisition, etc.) based on the true parallelism of FPGA via a simple graphical interface.

The graphical interface:

• Is easy to use
• Enables fast FPGA hardware programming (see Figure 1)
• Draws on a large body of FPGA solving building blocks (see Figure 2 and Figure 3)
• Verifies the FPGA solution at each step
• Is an end-to-end solution resulting in compiled code being loaded into the target FPGA

* DPD Digital pre-distortion is used to pre-distort the signal going into a power amplifier to accommodate for non-linearity as the chip approaches the max power. Data compression is needed due to the high data throughput of current ADC and limitations of Data bandwidth from digitizer to host using PCIe x4 Gen2

Fig1

Figure1 Avoid FPGA labyrinth

By design, the control of the main digital interfaces is kept out of the reach of the customizable area of the FPGA. This enables non-expert and expert users to be able to focus on the following tasks.

Non-expert users can (non-HDL programmers):

• Take benefit of the ready-to-use M3602A block library and the IP Core blocks of the library yet achieving full FPGA bandwidth performance (non-performance penalty).
• Access custom processing functions or algorithms with M3601A HVIs, bringing off-the-shelf, inter-module synchronization, phase coherence channel capabilities, and time deterministic real-time processing.
• It is also possible to free-up FPGA programming space for customer code so that users can build on the products core capabilities or add in their custom code into the FPGA with faster project deployment and no FPGA performance penalty.

Expert-users can:

• Access custom processing functions or algorithms with M3601A HVIs, bringing off-the-shelf, inter-module synchronization, phase coherence channel capabilities, and time deterministic real-time processing.
• Import existing IP developed in expert low-level FPGA programming tools such as VHDL, Verilog or Xilinx ® VIVADO/ISE projects, Xilinx CORE Generator IP Cores or include MATLAB/SIMULINK® code.

• Take benefit of the ready-to-use M3602A block library and the IP Core blocks of the library yet achieving full FPGA bandwidth performance (non-performance penalty).

Workflow

In addition to the faster compiling, it features hot programming capability where a module can be hot programmed with existing compiled code via PCIe without rebooting the instrument.

Referring to figure 2:

1. User opens an M3602A hardware project
2. Assembles the solution (see also figure 3)
3. Compiles using a cloud server and generates the binary
4. Hot programming: binary is loaded into the FPGA of the hardware

Fig2

Figure2 M3602A workflow

Figure3 shows the relation between the different types of blocks available in M3602A. The control of the main digital interfaces is kept out of the reach (locked FPGA features in the FPGA project) of the customizable area of the FPGA

A Hardware project integrates some locked blocks such as the Hardware blocks and Hardware ports which are integrated into the control system of the digital interface. A description of the different functional blocks is included below:

Hardware block: These blocks are an integral part of every hardware project. They can be used with the M3602A system design environment to create custom FPGA solutions. These blocks come along with the purchased hardware module. They have been designed to work together with the colored blocks described as follows when creating a custom FPGA solution.
Associated with the hardware blocks are hardware ports as shown in Figure 3. These ports are locked so that the user cannot remove them. They are only available in hardware projects and are responsible for communications between the internally configurable FPGA part (the FPGA customizable space which user can edit) and the rest of FPGA.
• Library block: These blocks are provided with every new project. They are generally simple and provide commonly used FPGA functionality.
• User block: These blocks are created and saved by the user using different FPGA vendor tools or from source code directly. These blocks can be imported to the project using the Block Editor. The user is the owner of these blocks which can be used them for extending or creating specific functionalities to create the FPGA solution.
• FPGA user block: This block is designed in the M3602A system design environment using the FPGA Block Project application.
• FPGA vendor block: This block is available for purchase from third party vendors. Powerful functional blocks can be added to the solution considerably reducing development time. The M3602A integrates their importation into the project and facilitates their management.
• Associated with the FPGA Block Projects are Library ports. These ports are configurable so as to interface with other blocks in a hardware or other FPGA Block project.
  

Figure3 Ports, blocks and Project relations